1. Field of the Invention
This invention relates to a semiconductor memory device such as a ROM (Read Only Memory).
2. Description of the Prior Art
Generally, semiconductor memory devices are tested by checking whether the intended data can be obtained for input of a particular address signal, thereby distinguishing between good and bad ones. In recent years, with advances in miniaturization techniques, the memory cell area has been further reduced, which in turn has led to an increase in the failure rate attributed to short circuits between adjacent word lines or between adjacent bit lines within the memory array because of processing effects. In the prior art, verification of such failure has been accomplished by sequentially reading every address location and thus determining the result.
However, such verification methods has the disadvantage of requiring a prolonged test period, which even further increases with the increase of the memory capacity being expanded.